An adaptive electronic output buffer system having a set circuit which includes a set output and a buffer circuit which includes a signal input, a signal output and a set input which is connected to the set output, the set circuit generating a set signal on its set output in order to counteract the effects of the manufacturing process variations and operating conditions on the output conductance of the buffer circuit.
The design of a buffer circuit is inter alia aimed at the charging and discharging of a capacitive load on the output within a specified period of time. On the basis of this requirement, a minimum value can be determined as regards the conductance of the buffer output. For the design of a buffer circuit satisfying this requirement as regards the output conductance, it is also necessary to take into account variations in the manufacturing process and the operating conditions (temperature, supply voltage) in which the design is to be used. The design is based on the least favorable combination (the so-called "worst case") of manufacturing process variations and operating conditions. Such a worst case combination will generally not occur in a realized design. The buffer will usually be overproportioned, which means that the output conductance and the output currents will be larger than calculated for the design. Switching operations then give rise to fast current variations (dI/dt) and voltage peaks across the inductances of the supply lines. These pulses reduce the intereference margin in digital circuits and may even cause incorrect switching and hence a loss of information in memory cells.
U.S. Pat. No. 3,970,875 describes a circuit in which an analog control signal sets a buffer in order to compensate for the effect of the process variations and the operating conditions. This circuit controls the charging current on the output of a static dissipating buffer; the discharging current cannot be controlled. Moreover, the extent of the control range can not be selected at random.